The present invention relates to a mechanism for transferring data between two devices in a data processing system and, more particularly, to a system for facilitating fly-by direct memory access (DMA) data transfer.
Historically, in digital data processing systems, great amounts of data had to be transferred between peripheral devices and memory. In these systems the central processing unit was responsible for transferring data between memory and peripheral devices under program control. Such data transfer systems were slow because for each byte of data transferred, the central processing unit had to fetch and execute the many instructions required to accomplish a transfer. Also, the central processing unit could not tend to other tasks while it wa involved with transferring data.
Eventually, a direct memory access facility replaced the slower program controlled data transfer between a device and memory. In data processing systems in which two devices transfer data between one another over a communications bus, the use of direct memory access devices is now well known. The direct memory access facility allows data to flow directly from memory to a particular device unattended. This data transfer mechanism is called flow-thru.: In other words, central processing unit control is no longer required after the initial data location is identified and the quantity of data is determined. When a device is to access data in memory, the DMA unit, disposed between the device and memory, controls the data transfer therebetween.
The DMA unit typically has a temporary storage register for buffering data from memory that is transferred to the device in order to have such data available for the device when needed. Thus, in typical DMA read operations, data at a particular address in memory is transferred (read) from the memory to the temporary storage register of the DMA unit and thence from the temporary storage register to the requesting device. Likewise, in typical DMA write operations, data is generated by a device, transferred to the DMA temporary register, and then retransmitted to the appropriate location in memory for storage therein.
More recently, a so-called fly-by technique has been developed by which a temporary storage register in the DMA unit is no longer required. In fly-by DMA read data transfers, data is read from memory and transmitted to the requesting device under control of the DMA unit but is not stored in a temporary storage register thereof. The fly-by transfer mode requires that there be separate read and write controls for both source and destination. Fly-by DMA write operations work in a similar fashion.
Dynamic Random Access Memory (DRAM) devices are frequently used in systems because of their low cost and high density. In order to access a location in memory, the address of the location must be supplied to the device along with appropriate control signals.
In order to optimize the internal layout of the memory and minimize pin count of the device, it is desirable to supply the address of the desired memory location in two parts called row and column addresses, using the same set of pins. Row Address Strobe (RAS) and Column Address Strobe (CAS) clock signals indicate the presence of row and column addresses on the pin and are used by the internal logic of DRAM devices to latch the address internally. An additional control signal called Write Enable (WE) is used to indicate whether the desired memory access cycle is a read cycle (WE inactive) or a write cycle (WE active).
By organizing the memory in an array of rows and columns, successive memory locations fall in the same row until all elements of that row have been accessed. Also, whenever any bit in a row is accessed, internally the whole row is accessed and brought outside the memory array. Then the selected column bit, as identified by the column address strobe, is supplied to the requesting device. If the row address of the next access is the same as that of the previous access, the next location can be selected simply by applying the column address of that location and activating the CAS control line. This technique is known as running a CAS cycle.
Unfortunately, a minimum off-time exists between two consecutive CAS cycles. Moreover, data setup and hold time requirements for the requesting device necessitate a predetermined length of time between memory accesses if the conventional fly-by technique is used. More importantly, they cannot be designed to work with the same minimum cycle time. This is due to the fact that the transmitting device has incompatible data output and data turnoff delay and the receiving device has incompatible data setup and data hold times.
It would be advantageous to provide a system of data transfer in a DMA environment using an improved fly-by technique.
It would also be advantageous to provide a system to start a read operation of data in a DRAM and to capture this data quickly.
It would also be advantageous to provide a system for transferring data in which the data captured from a data communications bus could be redriven onto the bus within one cycle.
It would also be advantageous to deactivate the CAS line while data is being redriven on the data bus, thereby allowing the CAS line to be reactivated in a shorter than usual period of time.